Inventory
Provided is a list of generator files with descriptions:
- Top level ADC
Generator: sar_sync_bootstrap.py
Specs (8 bit): specs_slice_sync_bootstrap.yaml
Specs (4 bit): specs_slice_sync_bootstrap_small.yaml
- Bootstrapped Sampler
Generates sampling switch
Generator: sampler_top.py
Specs: specs_lay_sample_top.yaml
- Synchronous Logic
This block is hierarchically put together in units
Generator (for all blocks): sar_logic_sync.py
- Specs:
For top level: specs_logic_sync.yaml
For array: specs_logic_array_sync.yaml
For unit: specs_logic_unit_sync.yaml
For OAI logic gate in unit:
- MIM Cap DAC
This block generates a capacitor dac of MIM caps
Generator (for all blocks): sar_cdac.py
- Specs:
For cap DAC: specs_cdac_mim.yaml
For switch bank: specs_capdrv_unit.yaml
For single MIM capacitor: specs_cap_mim.yaml
- Comparator
This block contains a wrapper around a comparator. A strongARM is used.
Generator: sar_comp.py
Specs: specs_comp_sa.yaml
- Clock generator
Divides input clock for a reset/sampling signal and provides buffering for clock signals
Generator: clk_sync_sar.py
Specs: specs_clkgen_sync_sar.yaml
- Digital blocks
Contains BAG generator code for some standard logic gates (inv, nand, flip flop, latch, etc.)
Generator: digital.py
Does not have any dedicated yaml files. Specified when used in other files
- Util Folder
Contains layout helper functions